1. Field of the Invention
The present invention generally relates to the field of semiconductor memories. More specifically, the present invention relates to high-density DRAMs.
2. Discussion of the Related Art
Generally, a DRAM is formed of an array of elementary cells placed at the intersection of rows or word lines and of columns or bit lines.
As illustrated in FIG. 1A, such an elementary memory cell is formed of a capacitive memory point (capacitor) MP and of an element T for controlling the memory point, generally a MOS transistor. The gate of transistor T is connected to a word line WL of the cell. The source or drain of control transistor T is in contact with a first electrode of memory point MP, the other electrode or plate of which is common to all the cells of at least one column and is biased to a very steady plate voltage VP. The drain or the source of control transistor T is connected to a bit line BL common to all the cells of a column.
As an example, as illustrated in the top view of FIG. 1B, it will be considered in the following description that the memory cells are formed by groups of two in active areas A of a semiconductor substrate. Each active area A is rectangular, its largest side being vertical, along the column axis. Two MOS transistors of the same type and dimensions are formed in active area A to have a common drain or source region. A bit line contact BLC is formed on this common drain or source region. Contact BLC is shown at the center of active area A by a cross in a square. The gate of each transistor runs on one side of contact BLC. These gates are insulated lines represented by hatched horizontal areas. Each one forms the word line of a cell. Each end of active area A corresponds to a source or drain region of each transistor in contact with an electrode of a memory point MP. Each memory point MP is represented by a square indicating contact MPC with the source or drain region and, around contact MPC, by a parallelogram in dotted lines symbolizing the capacitor surface.
Designating by F the smallest possible dimension for a conductive line, which is also called the minimum rule since it corresponds to a drawing rule imposed to the designer for a manufacturing technology, square F2 of minimum rule F then being the minimum surface area or unity surface area of a pattern, elementary cells with a surface area four times as large as the unity surface area (4F2) could theoretically be formed. In practice, the cells have a greater dimension generally on the order of eight times the unity surface area (8F2).
To form DRAMs based on elementary cells identical to those in FIG. 1A, it has first been provided to repeat an elementary pattern formed of an elementary memory cell.
FIG. 2A schematically illustrates the arrangement of the DRAM thus obtained. In such an array, any intersection of a row WLl, WLl+1, WLl+2 and of a column BLj, BLj+1, BLj+2, BLj+3 includes an elementary memory cell represented by a point. Each bit line BLj, BLj+1, BLj+2, BLj+3 is connected to an input of a respective sense amplifier SAj, SAj+1, SAj+2, and SAj+3. To enable reading, a second input of each amplifier SA is connected to a reference line RBL.
As illustrated in FIG. 2B, the forming in integrated form, in a semiconductor substrate of such an array then consists of repeating in the row (horizontal) direction as well as in the column (vertical) direction the structure described in relation with FIG. 1B.
A problem in this type of structure is the placing of sense amplifiers which require a width greater than that of a column. Another problem is the fact that the reference line(s) are independent from the bit lines and exhibit a noise which is not correlated with the noise therein.
To overcome these problems, a second type of memory such as illustrated in FIG. 3A has been provided, the elementary pattern of which extends over two rows and two columns and only includes two columns. Two adjacent bit lines of a same pattern respectively receive a signal and its complement. The two cells of a pattern are arranged so that each of the two rows and each of the two columns of the elementary pattern includes a single cell. As compared to an array of the first type described in relation with FIG. 2A, a row or a column of same dimension of an array of the second type includes half as many cells, an intersection out of two with a line or a row, respectively, being empty. Further, in the vertical direction, two adjacent patterns are arranged symmetrically. Thus, the word lines are arranged in order WL0, WL1, WL3, WL2 . . . WL2k, WL2k+1, WL2k+3, WL2k+2 . . .
FIG. 3B illustrates, in top view, the forming according to the technological process defined in FIG. 1B of a memory of the second type. More specifically, FIG. 3B illustrates the forming of the array portion including the intersections of the four rows WL2k, WL2k+1, WL2k+3, WL2k+2 and of the four columns BLt, {overscore (BL)}t, BLt+1, and {overscore (BL)}t+1 of FIG. 3A.
The elementary cells of a same column are aligned. However, from a given column BLt to the next one {overscore (BL)}t, the active areas in each of which are formed two cells are shifted so that word lines WL2k+1, WL2k+3 of column BLt can cross the next column {overscore (BL)}t above an insulating area separating two active areas.
As illustrated in FIG. 3C, to enable passing between two active areas of two conductive lines WL2k+1, WL2k+3, while minimizing the bulk, rows (word lines) WL2k, WL2k+1, WL2k+3, WL2k+2 are given a zigzag shape. With this arrangement, the elementary cell of a memory of the second type exhibits a theoretical surface area of eight times the unity surface area (8F2), in practice from ten to fourteen times said surface area.
Upon access to a cell of a given row WL2k+1 at the intersection with a given bit line BLt, the neighboring bit line {overscore (BL)}t for which the considered row WL2k+1 includes no cell is used as a reference line. Conversely, for the preceding row WL2k or the next row WL2k+2, upon access to the cell of this row placed at the intersection with bit line {overscore (BL)}t, the neighboring bit line BLt is used as a reference bit line. Thus, each elementary column pair BLt, {overscore (BL)}t or BLt+1, {overscore (BL)}t+1 of the array is connected to a sense amplifier SAt, SAt+1. There thus is one sense amplifier for two columns and no longer one per column as in the first type of memory.
Such a use as a reference bit line of a neighboring line enables in the first place recovering the surface area used in a memory of the first type by the reference line to form memory cells. In the second place, to form sense amplifiers of the same dimension, the space occupied by two columns instead of one in the case of an array of the first type is now available. Further, the number of sense amplifiers is reduced by half as compared to a memory of the first type. The column length can then be increased. In the third place, the fact of forming bit line BLt, {overscore (BL)}t, BLt+1, {overscore (BL)}t+1 and its corresponding reference line {overscore (BL)}t, BLt, {overscore (BL)}t+1, BLt+1 in a same array enables them to have a correlated noise. The densities and access performances of memories of the second type are thus improved with respect to memories of the first type.
A problem with this type of structure is that, as technology advances, as the dimensions of elementary cells and of the metallizations forming the word lines are reduced, it becomes impossible to form zigzag lines such as shown in FIG. 3C. A design of the type of that in FIG. 3B must thus be used again and the theoretical space gain resulting from the reduction in line dimensions is lost.
The present invention accordingly aims at providing a DRAM which combines the advantages of memories of the first type and of the second type.
The present invention aims at providing such a memory in which the elementary cells exhibit dimensions as close as possible to those of the cells of a memory of the first type.
The present invention also aims at providing such a memory having an increased density as compared to a memory of the second type.
The present invention also aims at providing such a memory having an access (read/write) reliability which is at least equal to that of a memory of the second type.
The present invention also aims at providing such a memory wherein the capacitive coupling between lines is reduced.
The present invention also aims at providing such a memory of simple manufacturing.
To achieve these and other objects, the present invention provides a DRAM formed of an array of cells, each of which includes a capacitive memory point and a control transistor, the array being formed of the repetition of an elementary pattern extending over three rows and three columns and including six cells arranged so that each of the three rows and each of the three columns of the elementary pattern includes two cells. Each column of the elementary pattern includes a first and a second bit line, each first and second bit line being connected to one half of the memory cells included by the column.
According to an embodiment of the present invention, at least one of the ends of the group of three columns of the elementary pattern is connected to a read device for selecting, based on the address of a cell, the bit line including the cell and the corresponding reference line.
According to an embodiment of the present invention, the read device includes access means for selecting, based on the address of the row including the addressed cell, the two bit lines that include the cell and at last one corresponding reference line and a means for validating the output of that of the access means enabling access to the bit line including the addressed cell.
According to an embodiment of the present invention, the access means include a sense amplifier and a multiplexer.
According to an embodiment of the present invention, for an addressed cell, the reference line is that of the first and second bit lines which is not connected to said addressed cell.
According to an embodiment of the present invention, the first and second bit lines altogether take up three metallization levels, each of the first and second bit lines partially taking up the first and third ones of the three levels, the crossings occurring via the second one of the three levels.
The foregoing objects, features and advantages of the present invention, will be discussed in detail in the following non-limiting description of specific embodiments in connection with the accompanying drawings.